Review and Analysis of Glitch Reduction for Low Power VLSI Circuits

Glitch Power Minimization Techniques in Low Power VLSI Circuits

Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is...

Glitch Power Reduction for Low Power IC Design

Because of the rapid growth of portable electronics, high density integrated circuits with low energy consumption and low electromagnetic interference (EMI) at high speeds are needed. It is well known that dynamic power dissipation is directly related to the number of the signal transitions in the circuit. Functional signal transitions are desirable, where spurious transitions (or glitches), ca...

Optimization Techniques for Low Power VLSI Circuits

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages

The advancements and scaling in technology are continuously increasing in accordance with Moore’s Law. This results in an increase in the performance of chips, but comes with a price due to the increased power consumption, and hence resources are spent on cooling, packaging and other methods to reduce the after effects. This additional cost has to be eliminated, and the most obvious solution is...